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Home Technology Technical Capability Statement - In Detail

QualiEco Technology

Simple but Smart solutions is our expertise... We believe in being one step ahead in technology and innovation at all times!!! Technical Capability Statement - In Detail

Prototype PCBsStandard PCBsDescription

TOPPCB Details
  • Max. no. of layers1818
  • Max. board size (L x W) in mm650 x 305650 x 305
  • Max. board thickness (in mm.)3.20 mm3.20 mm
  • Min. finished board thickness (in mm.)0.40 mm (No HAL)0.40 mm (No HAL)
TOPBase Material
  • (A) Base MaterialFR4FR4
  • (B) Inner layer Copper cladding  
  • * Max. Cu Wt. For Planes (Oz.)33
  • * Max. Cu Wt. For Signals (Oz.)22
  • * Min. Cu Wt. (Oz.)0.50.5
  • (C) Outer layer Copper cladding  
  • *Max Cu Wt. (Oz.)36
  • *Min Cu Wt. (Oz.)0.50.5
TOPEtching
  • Minimum (in mils)Trace WidthSpacingTrace WidthSpacing
  • Max. board size (L x W) in mm5555
  • Max. board thickness (in mm.)6666
  • Min. finished board thickness (in mm.)7777
TOPDrilling
  • Min. finished via hole size12 mils10 mils
  • Min. finished via pad size20 mils18 mils
  • Min. annular ring (via holes)4 mils4 mils
  • Min. annular ring (Component holes)8 mils8 mils
  • Min. hole size tolerance (in mils)PTHNPTHPTHNPTH
  • Hole size < 0.024"+/- 3+/- 2+/- 3+/- 2
  • Hole size > 0.024" < 0.138"+/- 4 +/- 3 +/- 4 +/- 3
  • Hole size > 0.138"+/- 6+/- 6 +/- 6+/- 6
  • Blind & Buried vias manufacturableYESYESYESYES
  • Drill to track clearance for inner layers14 mil14 mil10 mil10 mil
TOPPlating / Surface Treatment
  •  Trace WidthSpacingTrace WidthSpacing
  • HASLYESYESYESYES
  • Electrolytic GoldYESYESYESYES
  • Electroless Nickel / GoldYESYESYESYES
  • SMOBC with OSP (Entek Coating)YESYESYESYES
  • Immersion SilverYESYESYESYES
  • Immersion TinYESYESYESYES
TOPLayer construction & Impedance Design
  • Min. core thickness8 mils6 mils
  • Preferred varieties of Thin core laminates generally stocked (in mils) 8, 14, 288, 14, 28
  • Prepregs generally stocked (in mils)4, 74, 7, 2.5
TOPMaximum Fabrication Tolerance
  • Maximum Fabrication Tolerance+/- 10%+/- 8%
TOPSolder mask
  • Solder maskXXX =XXX =
  • Mask opening (pad + XXX)8 mils6 mils
  • Min. solder mask web width between pads4.5 mils4 mils
  • PAD to PAD min. space if web required12.5 mils12 mils
  • SM clearance to PAD4 mils4 mils
  • Min. SM thickness18 mils18 mils
TOPComponent Reference (Silk Screen)
  • Legend (Silk Screen) line width9 mils5 mils
  • Min. character height55 mils40 mils
  • Min. character spacing8 mils6 mils
TOPElectrical Test
  • CAD net list testing (IPC356D)PossibleNot Possible
  • Min. SMD pitch testable20 mils12 mils
  • Min SMD pad width testable8 mils6 mils
  • Max testing area (mm x mm)410 x 350 
  • Testing voltage40 volts240 volts
  • Open resistance> 10 K ohms 
  • Short resistance5 ohms to 10 K ohms 
  • Top and Bottom Test simultaneouslyPossiblePossible
TOPControlled Impedance measurement
  • Controlled Impedance measurement50, 100 ohms50, 100 ohms
TOPInner Layers (VCC and GND Layers)
  • Minimum Isolation from finished Drill  
  • Up to 8 Layers (Single Stage bonding)0.45 mm0.45 mm
  • Up to 8 Layers (Two times bonding)0.60 mm0.55 mm
  • Up to 8 layers (more than two times)0.80 mm0.75 mm
  • Above 8 layers(Single Stage bonding)0.80 mm0.75 mm
  • Min. Annular ring for thermal pads4 mils2 mils
  • Min. Thermal Air Gap0.25 mm0.25 mm
  • Cu area to PCB edge clearance0.50 mm0.30 mm
TOPInner Layers (Signal Layers)
  • Minimum Annular Ring5 mils4 mils
  • Finished Drill to Track clearance  
  • Up to 8 Layers (Single Stage bonding)0.45 mm0.40 mm
  • Up to 8 Layers (Two times bonding)0.60 mm0.55 mm
  • Up to 8 layers (more than two times)0.80 mm0.75 mm
  • Above 8 layers(Single Stage bonding)0.80 mm0.75 mm
  • Cu area to PCB edge clearance0.50 mm0.30 mm
TOPScoring (V-cut)
  • Score line to Cu area clearance> 0.40 mm0.40 mm
TOPRouting
  • Minimum router diameter1.2 mm*1.0 mm*
  • Cu area to PCB edge clearance (Outer Layer)0.3 mm0.25 mm
  • Cu area to PCB edge clearance (Inner Layer)0.50 mm0.40 mm
  • * 0.8mm & 0.9mm router sizes also available and can be used for thin slots

 

1. Acceptance on manufacturability of Blind and buried vias will be given after studying Multi Layer
   construction / Inner layer design.
2. We prefer min. pad size >= hole size + 0.50 mm for any PTH hole.
3. NPTH holes should preferably not have any pad around them.
4. Jump scoring and depth routing possible – conditions apply

PCB Design Tips

Product Comparision Chart

We have capability to manufacture Single Sided/Layer (SS), Double Sided/Layer (DS-NPTH & DS-PTH) and MultiLayer (up to 24 layers) PCBs with RoHS as an option.

Compare Low Cost Prototype with Standard Prototype and Production. Choose one which
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PCB Design Tips

PCB Design Tips

When designing a PCB, try to limit
the amount of draws you use.
Draws use a lot of memory and slows the programming time. Ex.: Use a flash for pads instead of draws. If for some reason we need to increase or decrease that pad size, it can easily be done by changing the D-code but if they are done with draws it could be a nightmare.

Learn more